Senior FPGA Systems Engineer — EW Countermeasures

Architect high-speed DSP on FPGAs for cognitive frequency hopping: direct RF sampling, spectrum filtering, and anti-interference SDR codecs.

When the spectrum is contested, links live or die on microseconds. You will architect the high-speed DSP — direct RF sampling, filtering, and cognitive frequency hopping — that keeps telemetry flowing through barrage jamming. Working closely with veteran radio operators, you will reverse-engineer enemy EW signatures and turn them into firmware that stays one step ahead on Xilinx/AMD UltraScale silicon. The feedback loop here is unusually short: what you tape out can be on a range within days.

• Verilog/SystemVerilog/VHDL on Xilinx/AMD UltraScale
• SDR architectures, ADC/DAC, FFT/IFFT filters, GNU Radio
• Strong grasp of RF physical layer, FHSS, and OFDM
• Comfort with spectrum analyzers and SDR lab benches

• Develop microsecond-class frequency-hopping firmware
• Write DSP blocks that extract clean telemetry from jammed spectra
• Debug signal-integrity anomalies on prototypes
• Work with veteran radio operators to dissect enemy EW signatures